Espressif Systems /ESP32-S3 /UHCI0 /INT_RAW

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Interpret as INT_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_RAW)RX_START_INT_RAW 0 (TX_START_INT_RAW)TX_START_INT_RAW 0 (RX_HUNG_INT_RAW)RX_HUNG_INT_RAW 0 (TX_HUNG_INT_RAW)TX_HUNG_INT_RAW 0 (SEND_S_REG_Q_INT_RAW)SEND_S_REG_Q_INT_RAW 0 (SEND_A_REG_Q_INT_RAW)SEND_A_REG_Q_INT_RAW 0 (OUT_EOF_INT_RAW)OUT_EOF_INT_RAW 0 (APP_CTRL0_INT_RAW)APP_CTRL0_INT_RAW 0 (APP_CTRL1_INT_RAW)APP_CTRL1_INT_RAW

Description

Raw interrupt status

Fields

RX_START_INT_RAW

This is the interrupt raw bit. Triggered when a separator char has been sent.

TX_START_INT_RAW

This is the interrupt raw bit. Triggered when UHCI detects a separator char.

RX_HUNG_INT_RAW

This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value.

TX_HUNG_INT_RAW

This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value.

SEND_S_REG_Q_INT_RAW

This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers.

SEND_A_REG_Q_INT_RAW

This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers.

OUT_EOF_INT_RAW

This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data.

APP_CTRL0_INT_RAW

This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET.

APP_CTRL1_INT_RAW

This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET.

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